Barcelona K8L/K10 news thread

[Rahul]

January 23, 2007
AMD’s Road Leads To Barcelona
By Andy Patrizio

AMD (Quote) is itching for a fight with Intel, preparing for the next round of the server rumble with the upcoming Barcelona chip.

The No. 2 chipmaker is starting to release details about its next-generation server processor, the follow-up to its highly-successful Opteron chip.

Code-named Barcelona, the new chip is a quad-core design that tweaks the existing x86-64 processor architecture.

AMD expects to ship Barcelona chips by the middle of this year. In a meeting with internetnews.com this week, AMD officials emphasized several key differentiators over the Intel (Quote) quad-core server chip, the Xeon 5300, or Clovertown.

First, the Barcelona chip is a native quad-core design, not two dual cores glued together like the Xeon 5300, AMD officials claim.

The memory controller for Barcelona is built into the chip and not external, like the front-side bus design Intel uses, leading AMD to claim greater performance because the chip’s four cores are not getting bottlenecked going through one gateway.

Despite the big gain in performance over the previous generation, Barcelona will have the same power consumption levels, with 95- and 68-watt designs.

So even though the wattage hasn’t gone down, the increase in processing power turns into a 60 percent-per-watt performance gain, according to Randy Allen, vice president of the server and workstation division at AMD.

Allen said there’s an 80 percent scale over dual core processors; AMD’s own benchmarks put it well ahead of the Xeon 5300 in terms of performance.

“We took their best punch with Clovertown and this is our response,” he said.

Second, AMD designed the hardware to be easily upgraded. An existing Opteron server can be upgraded by removing the old processors, placing the new Barcelona chip in the socket, and performing a BIOS (define) upgrade.

AMD also took pains to support virtualization by working with VMWare, Xen and Microsoft to create AMD-V the company’s hardware-assisted virtualization technology.

Barcelona also tweaks the existing design of the x86-64 processor, but those tweaks are significant.

Streaming SIMD Extensions (SSE) have been expanded from 64-bits to 128-bits; the data cache bandwidth has been doubled to 2x 128 bit loads per cycle; and the L2 cache bandwidth has also doubled, to 128 bits per cycle.

Also, the memory controllers now support full 48-bit addressing, which could allow for up to 256 terabytes (define) of physical memory. Yes, 256TB of memory.

The AMD architecture has also been designed from to operate in a multi-processor, multi-core environment, so its scalability is not the issue facing the company, said Dean McCarron, president of Mercury Research.

AMD’s problem is building it. Intel has a distinct advantage in manufacturing. It can make more chips, make them faster and make them smaller. AMD won’t be using a 45-nanometer die size until the end of the year, while Intel is already on 45nm.

So it becomes a competition of trade-offs.

“AMD will have the architecture that tips the balance of scalability in their favor, but Intel has the manufacturing and pricing advantage,” McCarron said.

But he added, AMD is in a significantly better position now than it was in 2003, when Opteron was introduced and it had no server share and no OEMs. Since then, it has signed up Dell (Quote), IBM(Quote), HP (Quote), and Sun(Quote).

“The inroads they’ve made in servers have been impressive. They went from zero to a respectable share. That’s the reason we are in the environment we are in today, which is both companies being competitive,” said McCarron.

AMD stock dropped four percent today after it reported earnings for the fourth quarter of 2006.

From here

AMD’s native quad-core design picks up more steam

In a series of memos forwarded to DailyTech, industry insiders discussed the upcoming launch frequencies regarding AMD’s next-generation architecture, previously dubbed K8L by AMD Executive Vice President Henri Richard. Since then, AMD has generally referred to the next-generation chips as the Barcelona family, although Barcelona specifically denotes the high-performance quad-core server processor codename.

Some details of next-generation AMD desktop processors, the Stars family, were revealed late last year.

The desktop equivalent of Barcelona, codenamed Agena, is the 65nm flagship of AMD’s next-generation desktop processors. Launch frequencies were quoted at “2.4 - 2.6GHz.” Previous roadmaps had indicated Agena would debut at 2.7 to 2.9 GHz. Agena will have a 2MB L2 and 2MB L3 cache per CPU. AMD’s internal guidance denotes this as a 125W TDP processor. As the flagship, Agena will be the first next-generation desktop launch and is scheduled for Q3’07.

Kuma, the dual-core mainstream next-generation desktop processor was quoted as having launch frequencies of “2.0 - 2.9GHz.” Unlike the quad-core Agena processors, Kuma will feature 1MB of L2 and 2MB of shared L3 cache. Kuma will launch with both 89W and 65W TDP variants, but Energy Efficient models scheduled for 35W TDP will follow shortly after.

Rana, the next-generation Sempron successor codename, will launch with frequencies in the 2.1 to 2.3 GHz range. The dual-core CPUs will feature 1MB of total L2 cache, but no L3 cache. Rana’s TDP is rated at 65W. Rana will not launch with the Agena flagship; AMD roadmaps have the processor launching at the same time as the Energy Efficient Kuma processors, or approximately Q4’07 if the launch schedule holds together.

As previously reported on DailyTech, Stars processors will use AM2+ motherboards. These processors can plug into existing AM2 motherboards today given the proper BIOS updates, but without the AM2+ sockets Stars processors will drop down to the HyperTransport 1.0 bus speeds.

AMD’s Agena FX codename also appears to still exist on the roadmap. The only difference at this point between Agena and Agena FX is that Agena FX will use the Socket 1207+ interface.

From here

AMD WASN’T JOKING about Barcelona hitting Q2. I didn’t believe it until a solid source came out and said the volume ramp is starting ‘really soon’.

If really soon is defined as the end of the month, and you add in the 10-12 weeks it takes from shiny silicon pizzas in to pin laden chunks out, that would mean parts are available at the beginning of May.

It would not surprise me if it is trading yield out for time to market, so let’s add a month before they are really available. That puts things at early June for volume, or when AMD said it would have it out. Minor miracles do happen. µ

From here

[Rahul]

As most of us know Socket AM3 was planned to introduce together with AMD’s next-generation K8L architecture as well as the new Quad Core, recent news from the industry tells AMD has changed its mind. Sources said Socket AM3 is postponed to mid-2008, and that the new socket AM2+, an upgrade version to AM2, is now introduced to the new K8L processors and Quad Core instead of AM3. Friends from the industry said AM3 will be available till the market of DDR3 is well developed, a kind of passive strategy.

According to the previous plan, K8L processors as well as the new Quad Core are both based on Socket AM3 with build-in DDR2/3 memory controller, and are compatible with the existing AM2 main board. Yet AMD has decided to postpone AM3 as they reviewed the market trend of DDR3 memory.

According to the latest roadmap for memory module from Samsung, DDR3 is ready right now, where samples of DDR3-800/1066/1333 have been sent to related partners. DDR3 is expected to be available in Q2 2007 with 70nm manufacturing process, and soon to replace DDR2 in mid-2008. It’s clever to put down the non-common DDR3 support into the processors as it complicated the design as well as increased the cost. Releasing the DDR3 supported AM3 till mid-2008 is somewhat reasonable. Besides, as Socket AM3 don’t support AM2 processors, it’s expected AM3 would share only 10% of the total shipment after the release. Actually, AM2+ is beneficial to end user as well as manufacturers for cost saving.

In principle, Socket AM2+ is 100% compatible to Socket AM2. The difference is only on the upgrade of Hyper-Transport to version 3.0, such that the I/O ability is doubled from 2GHz to 4GHz. With great compatibility of Hyper-Transport, whatever K8 or K8L processors will also be supported in both AM2 and AM2+ main board.

From here

[Rahul]

AMD Announces Quad-Core Opteron Server Chips

Advanced Micro Devices today showed a laboratory version of its promised “Barcelona” quad-core Opteron 8000 server chip to analysts gathered in Berkeley, California, and said it plans to begin selling the product in the second quarter of 2007.

AMD will pitch the chip to users of high-end, commercial workstations and servers. Users could see performance improvements of up to 70 percent in database applications and 40 percent in floating-point applications compared with AMD’s dual-core “Rev. F” Opteron.

The demonstration was AMD’s second effort to show that it is keeping up with quad-core chips from rival Intel. AMD also launched its “4x4” Quad FX Platform, a motherboard with two dual-core Athlon 64 FX-70 series chips intended for the desktop gaming market.

Chip Wars

Intel lost significant market share to AMD in 2006 as it endured criticism for being slow to produce chips that emphasized power efficiency instead of pure calculating speed. Intel has bounced back in recent months with the launch of dual-core chips including the Core 2 Duo for desktops and the Xeon 5100 “Woodcrest” chip for servers. On November 14, Intel reached the market first with quad-core chips, offering the Core 2 Extreme QX6700 for gamers and the Xeon 5300 for servers.

Intel has also led the industry in converting its chip designs from the 90-nanometer process to 65 nm, including all four processors mentioned above. In response, AMD has criticized Intel’s quad-core design as merely gluing two dual-core Woodcrest chips together, whereas the Barcelona chip includes all four cores on a single piece of silicon. Analysts are divided on the impact of that distinction, and say they cannot measure the difference until they compare benchmarks from both finished versions.

Barcelona Impact

Still, AMD trumpeted Barcelona today as an engineering achievement that marks the company’s shift to 65-nm architecture. By shrinking the processor die, AMD is able to improve power efficiency and squeeze an extra level of shared cache memory onto the design, said John Fruehe, AMD’s worldwide market development manager for server and workstation products.

“As you add more cores, it becomes less about brute force and more about the efficiency of how many things you can do at once, and how efficiently you can order them,” he said.

“From a customer perspective, those who will see the biggest bang for their buck with quad-core are people running applications like larger databases. The more threaded an application is, the more benefit you get.”

The users who will see the greatest return on their quad-core investment are users of multithreaded applications like CRM (customer relationship management), ERP (enterprise resource planning), e-commerce, and virtualization, Fruehe said.

AMD will first launch the Barcelona design on a four-socket board (running four quad-core chips) and a two-socket board (running two quad-core chips). The company will wait until later in 2007 to launch single-socket Barcelona boards, which will be used mainly to develop new applications for the larger servers or to run Web farms to handle multiple simultaneous processing requests.

AMD expects server vendors such as Dell, Hewlett-Packard, IBM, and Sun Microsystems to adopt the new technology for their servers in 2007, although none of those companies has yet made a public announcement.

From here

[Rahul]

AMD reinvents the x86

AMD’s next-generation processor line, code-named Torrenza, has gone from a block diagram to living, breathing silicon. The first incarnation of AMD’s redesigned x86 CPU is Barcelona, that which your non-co-readers will call quad-core Opteron. Barcelona is genius, a genuinely new CPU that frees itself entirely of the millstone of the Pentium legacy. It’ll do the same for you.Each of Barcelona’s four cores incorporates a new vector math unit referred to as SSE128 (128-bit streaming single-instruction-multiple-data extensions). I am aware that you only do quantum physics on weekends, but the potential for hardcore IT tasks such as encryption, compression, real-time analysis of high volumes of streaming business transactions, and wire-speed packet analysis is also the stuff of science fiction. Barcelona gives floating point operations their own schedulers (checkout lanes) and runs them twice as fast as 64-bit SSE did. AMD claims that Barcelona’s per-core floating point performance is more than 80 percent faster than the present Opteron. Benchmark that. And separating integer and floating-point schedulers also accelerates this thing called virtualization, which you may notice is a recurring theme for Barcelona.

Nested paging tables is a per-core feature that will light the afterburners on x86 hardware virtualization. A paging table holds the map that translates virtual memory addresses to physical memory addresses, and each CPU core has only one. Virtual machines have to load and store their page tables as they get and lose their slice of the CPU. AMD solved the problem with nested paging tables. Simplified, each VM maintains its own paging table that stays fixed in place. Instead of loading and saving paging tables as your system flips from VM to VM, your system just supplies Barcelona with the ID of the virtual machine being activated. The CPU core flips page tables automatically and transparently. This is another feature that’s implemented for each core.

Much fuss has been made about power efficiency, but the best of x86 power saving schemes is crude. They adjust the clock speed and the operating voltage of the entire CPU, and the selection of set points is small. Barcelona keeps this technique, but builds on it with inspiration from IBM and Transmeta. Barcelona blacks out power to individual portions of the chip that are idled, from in-core execution units to on-die bus controllers. This hasn’t made it into PCs before because it’s very difficult to manage light switches for several “rooms” individually and to make sure that, like a refrigerator light, whenever a door is opened, the light is on as if it’s been burning the whole time. Power savings from these schemes are dramatic. If Barcelona lacked this feature, it would still be a green CPU.

Unlike Intel’s Core, Barcelona gives each core dedicated L2 cache, and Barcelona incorporates a redesign that reduces cache latency (access delays). Barcelona adds Level 3 cache, a newcomer to the x86 and a page out of IBM’s POWER playbook. All four CPU cores in a Barcelona socket will share a single master catalog of recently-retrieved data. A three-level cache is a must-have for a multicore CPU, and that becomes obvious when you get a demo that switches L3 on and off.

Barcelona is a new CPU, not a doubling of cores and not extensions strapped on here and there. Get ready to be blown away long before its release, which is scheduled for midyear.

From here

[Rahul]

San Francisco (CA) - AMD unwrapped a few more details about its upcoming quad-core server and workstation processor “Barcelona” at the International Solid State Circuits Conference (ISSCC). While the announcements focus on the power efficiency of the processor, the company tells conference

attendees that it is confident about regaining the performance crown from Intel’s Xeon 5300 series processors.

With a launch date that is believed to be scheduled towards the end of the second quarter of this year, AMD has begun to build momentum around its first quad-core processor, code-named “Barcelona.” The new Opteron processor has the difficult task to stop the current freefall of dual-core Opteron average selling prices, put AMD back into a leadership position in the 2P server/workstation market and increase the firm’s advantage in the 4P+ systems market.

Not unexpectedly, many of today’s questions about Barcelona focus on the chip’s performance capability. Typically, the real world performance of server processors heavily depends on the applications they run, but AMD says that customers will see dramatic improvements when compared to dual-core Opteron processors as well as Intel’s quad-core Xeon 5300 (“Clovertown”). Opteron product manager Brent Kirby told TG Daily that Barcelona will outpace a dual-core Opteron by between 60 and 80% at any given clock speed. Compared to Intel’s fastest Xeon 5300 (X5355), AMD promises that will be about 40% faster in some applications.

What makes Barcelona especially interesting is the fact that the processor will be offered in the same power envelopes as today’s dual-core CPUs. Regular quad-cores will run at a thermal design power of 95 watts; “HE” versions will be rated at 68 watts and “SE” versions at 120 watts. Since Barcelona will use the socket F, companies can simply replace current socket F dual-core Opterons with the new processor, without having to worry about design or heat issues.

Intel’s quad-core series is rated at a TDP of 80 watts for processors with clock speeds between 1.8 GHz and 2.33 GHz; the 2.66 GHz model is rated at 120 watts. AMD claims that the typical TDP of its processors will be about 15% lower than the TDP provided - which would put the lowest power quad-core at a typical power consumption of less than 58 watts.

Among the new power savings features is another generation of the firm’s “PowerNow” technology. “Enhanced” PowerNow can dynamically adjust the voltage and clock speed of each processor core. Additionally, the processor is equipped with two separate power rails that enable Barcelona to reduce the frequency in the cores, but keep the memory controller running at full speed.

Shutting down parts of the processor that are not needed during certain periods of time plays an important role in the keeping the quad-cores thirst for power at a moderate level. AMD said that it has integrated “fine” and “course” clock gaters throughout the processor, which can either power down entire blocks or “increasingly” finer sections of the chip. There is also a new, platform-focused power management approach in the memory controller that can turn off the either the write or the read logic when not in use. AMD says this technique reduces the power consumption of the memory controller by up to 80% on “many” workloads.

AMD has not provided detailed specifications about the processor, but confirmed that Barcelona will integrate 2 MB of shared L3 cache as well as an improved virtualization feature that, according to AMD, can provide a performance gain of “up to 43% over non AMD-V driven applications.”

Pricing of the processors remains unclear at this time. However the company mentioned during its recent Q4 conference call that it plans on introducing the quad-core at similar price levels that were covered by the first dual-core Opterons. Kirby told TG Daily that AMD intends to move Barcelona quickly into all segments of the server market.

From here

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[Anish]

^ All looks solid on paper, enthusiasts will only buy if they can crack sub 5s timings on Pi with all the hyped up DDR3 support

[Rahul]

^^ lol dude world doesn’t end @ superPI … hehe

[sunbiz_3000]

AMD promises that will be about 40% faster in some applications…which application??

[gaganjain]

AMD promises that will be about 40% faster in some applications…which application??

which application?

i think mostly 3d

[ssdivisiongermany193]

let’s see AMd can crsuh Intel ,but peryn looks solid than barcelona

[sunbiz_3000]

and Nehelam…looks even stronger with the CSI!! AMD is slowly being pushed…and I think the future is really looking gloomy for AMD…

I guess Fusion is the only thing to save the AMD revenues!! But gosh!! Intel says it’ll do an addon graphics with Nehelam Thats something to look out for!!

[PoBoy]

techPowerUp! News :: AMD Barcelona/Agena FX’ TDP is 95W
Fudzilla - AMD’s quad core consumes 95W

Now as Fudzilla.com acts like their silent megaphone they tell the public that 95W will be the maximum TDP for Barcelona and Agena FX. That is quite low for a real quad-core CPU and sounds very promising in terms of overclocking achievements.
AMD’s upcoming Agena FX and Barcelona native quad core CPU’s will consume less than 95 Watts. We all expected more from this native quad core on 65 nanometre but I guess AMD pulled some kind of miracle.
…
It looks that a single core from this device would need less than 24 Watts and at some crazy speeds this is more than good result.

[thexfactor]

The integrated memory controller (IMC) will get a few new features in the K10 core. When utilizing multiple memory modules, along with proper BIOS implementation and mainboard routing, the IMC can access memory in 64-bit channels (72-bit if you use ECC). This way it is possible to read and write data simultaneously, or improve efficiency for irregular access patterns which increasingly occur in a quad-core environment. This feature is available on AM2+ and F+ boards; on "old“ socket AM2 and F boards the usual 128-bit dual-channel mode is available.

Due to split power planes, the IMC can be clocked down independently of the CPU cores, along with reduced voltage. This also enables CPU overclocking without touching the memory frequency, something that may appeal to enthusiasts. These features are again dependent on Socket AM2+ and F+ platforms.

Amato explained how the quad-core design benefits from the internal crossbar switch the backbone of communication inside the K10 CPU. With Intel’s current quad-core design there are cases where data needs to travel over the FSB – in AMDs case all inter-CPU communication takes place on-die.

The crossbar switch of the K10 core is already prepared for up to 8 cores, Amato boasted. Amato wouldn’t give even a vague timeframe for market availability of such a CPU, though he indicated the company is prepared for whatever the market demands. Amato made clear that octo-core is far away in the future – Shanghai will not get 8 cores.

K10 will introduce a shared L3 cache while the individual cores have dedicated L1 and L2 caches. As long as requested data lies in L1, it can be directly loaded. This also works if the data lies in the L1 cache of another core, in which case the communication works via the crossbar switch. In case requested data resides in the L2 cache, it will be loaded to L1 and then invalidated in L2 as AMD has an exclusive cache design. The L3 Cache, however, is not exclusive, but allows for a shared bit to be set. If a core loads data marked as shared, it will reside in the L3 cache and can be fetched by other cores as well.

Amato also mentioned an array of power saving measures which, in sum, allow AMD to deliver a quad-core CPU in the same thermal envelope as today’s dual-core CPUs.

K10 adds the capability of independently clocking all the CPU cores. In current K8 processors (and Intel’s Core 2 generation), all cores are clocked at the same level all the time – the P-state can only be changed synchronously. In case of a compute-intensive single-threaded process, all cores must run on the highest level P-state. On K10-based CPUs, the idle cores could be switched to the lowest P-state, while others are in different states, depending on load.

This feature could possibly be abused by overclockers to overclock a single core above the specified levels. Amato clarified that AMD doesn’t endorse overclocking, but acknowledges there are people interested in that. In a warranty case, AMD could detect PLL programmings out of spec which would deny the warranty. The new cores, however, have new thermal sensors, to improve overheating protection.

Amato closed the session by mentioning Shanghai as a successor to Barcelona in the server space for 2008. Shanghai will be an improved quad-core architecture, which is supposed to be socket-compatible with current Socket F platforms. Roadmaps available to DailyTech revealed Shanghaiis a 45nm quad-core CPU featuring 6MB of L3 Cache.

DailyTech - AMD Talks Details on K10

[200mph]

this news looks good… hope we get to see AMD running in profits again.

[PoBoy]

Fudzilla - K10, Barcelona scores up

We don’t have many numbers but at least in specfp_rate2000 Barcelona ends up a bit less than **50 percent faster **than Intel quad core codenamed Kentsfield.
We are quite sure that this is the best score but it definitely sounds impressive. AMD chaps are very confident that K10 marchitecture and native Quad core is the way to go and Intel will probably have to pay the price for duct taping its chips.

[PoBoy]

Fudzilla

… At 65 nanometre native quad core AMD can hit *45W TDP *and again challenge Intel with its energy efficient designs … The core that can hit these speeds will be clocked to 1.9 GHz or less but it’s still impressive. Some parts will have 68W TDP … this means that these parts will be supper overclockable after all …

[PoBoy]

Fudzilla

We told you before K10, Agena works just fine. … The Agena processor is an AM2 version and fits in 940 pin boards.
It works at 1.9 GHz or 1908 MHZ to be precise with multiplier at 9.5 and the bus speed of 200.9 MHz.
Agena at 1.9 GHz has 4x64KB L1 Data cache memory, 4x64KB L1 for Code, 4x 512 KB L2 cache and finally all cores share the 2048KB L3 cache.

[PoBoy]

Agena 1.9 GHz overclocks to 3.05 GHz

With the default multiplier set to 9.5, you can raise the FSB all the way up to 320 MHz … You only need to increase the voltage from 1.273 to 1.297V and you hit over 3 GHz or 3042 MHz to be precise. This is an 1142 MHz overclock or 62 per cent from the stock speed and the machine was stable at all times … So AMD’s native quad core is a really overclockable part, …

[PoBoy]

techPowerUp! News :: AMD Claiming 50% server advantage
Acc to a AMD press release …

AMD also disclosed updated performance projections for its upcoming native Quad-Core AMD Opteron™ processors, code-named ‘Barcelona.’ The new Barcelona projections are based on the latest SPECcpu2006 benchmarks and show that AMD expects to have up to a **50 percent **advantage in floating point performance and **20 percent **in integer performance over the competition’s highest-performing quad-core processor at the same frequency.

[MAGNeT]

AMD reckons Barcelona will be ‘50 per cent’ faster than Intel

AMD reckons Barcelona will be ‘50 per cent’ faster than Intel

AMD RECKONS its upcoming Barcelona quad-core Opterons will outperform Intel by up to 50 per cent. Chimpzilla claims that Barcelona’s SPECcpu2006 benchmark figures demonstrate a 50 percent floating point and 20 percent integer performance over current Intel quad core parts.

Randy Allen, AMD’s server and workstation veep, says the parts will be available in the Summer and we should expect more than four cores in the future. Allen added that the Opteron 2222 and 8222 SE dual core server chips are available in volume from today, priced at $873 and $2,149 respectively in 1,000 unit tray quantities.µ