s7e9h3n and I have been working on decoding the AMD memory controller/stepping information found on all new AMD processors for awhile now. This information is the combination of 5 letters and numbers found on the second line, immediately proceeding the year/week production code.
Example: CABNE
1st letter: "production/release code"
Pre-production or early samples have an "A" here where final production batches will be a "C" (for current chips). Some may recall that Venice samples where seen in the wild as "ABBLE" and current production runs are "LBBLE". While complete understanding of this is unknown at this time, it is clear that this has something to do with early samples.
2nd letter: "core cache code"
A = single core, 1MB
B = single core, 512KB
C = dual core, 1MB (each)
D = dual core, 512MB (each)
Note: 'Toledo' cores (1MB) with half the cache disabled will still be coded as "C". Therefore, you can see earlie 4600+ samples as ACXXX with only 512KB per core enabled.
3rd and 4th letters/numbers: "memory controller revision"
Works like a counter using all letter of the alphabet and digits 1-9. 3rd letter increments when running though all available 'steppings' as noted by the 4th letter.
FX-55: XXA2X
FX-57: XXBNX
FX-57 (new stepping)/FX-60: XXB2X
3700+ (new stepping): XXB3X
...
and so on...
5th letter: "revision code"
C = rev C (as in CG Clawhammers)
D = rev D (as in D0 for CBBID chips....)
E = rev E (as in the rev E 'San Diego' core)
-FCG & s7e9h3n
