There are several issues with the FSB that Intel has to work around to get the Conroe generation of products to be high performing. For example, while the highest speed on this bus is 266 MHz, only the data bus is quad pumped (giving the 1066 MHz number often bandied about). The address and command busses are still single pumped, so they essentially run at 266 MHz. The bus is also bidirectional, but not full duplex, which means that during any clock the data/address/command streams are traveling in only one direction. Once that is finished the bus switches back the other direction. Data does not simply stream in and out through the FSB, but rather it is a one way street at any one time, and when needed that street travels in the other direction.
While this worked fine for many generations of Pentiums, it is now looking far too creaky and slow to truly feed the new generation of Intel processors. The memory controller that is located on the chipset is running at chipset speed, not CPU speed. So for a 800 MHz FSB processor the memory controller is running at 200 MHz, but for a 1066 MHz FSB product the controller is running at 266 MHz. This is a far cry from AMD’s memory controllers that run from 1.8 GHz to 2.8 GHz.
The FSB is the main weakness behind this next generation of Intel parts. So how exactly is Intel getting around this? The easiest way is to include large caches on the processor. This is exactly what Intel has done. The Conroe series of chips will come with either 2 MB or 4 MB of cache per core. This means that in the standard desktop dual core Conroe chip, there will be 4 MB of L2 cache. On the possible Extreme Edition chip we expect to see a total of 8 MB of L2 cache. That is a lot of cache, and it takes up far more space than the actual core itself. On the AMD side L2 cache sizes go from 256 KB L2 on the Semprons to 1 MB L2 per core (2 MB L2 total) on the high end X2 chips.
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