The European Commission has awarded a €4.5m subsidy to a consortium of research institutes and commercial chipmakers to address the issue of leakage in current and future generation semiconductors.
The Controlling Leakage power in NanoCMOS SoCs (Clean) project aims to create new design methodologies, techniques and tools to automate elements of chip design work related to power conservation.
Leakage is wasted power that 'leaks' through the components inside the transistors on a chip.
While it is a known phenomenon, leakage is threatening future sub-65nm and low-power processors because these chips feature smaller components and significantly more transistors than previous models.
"The project will make a significant contribution in overcoming the technology shortcomings for 65nm and below, and in particular process variability and unreliability, as well as leakage currents," said lead project co-ordinator Roberto Zafalon, R&D programme manager at STMicroelectronics.
"The outcome of Clean will allow a decrease in the power consumption of nano-electronic devices and increase design productivity at the same time."
Intel admitted in November that it would be impossible to build a processor for mobile phones using current generation 65nm technology because the resulting leakage would drain the battery in minutes.
A typical desktop processor wastes about 25 per cent of its power due to leakage, according to Intel data. Processors such as the ones used in mobile phones waste up to 90 per cent and put only 10 per cent of power to good use.
The Controlling Leakage power in NanoCMOS SoCs (Clean) project aims to create new design methodologies, techniques and tools to automate elements of chip design work related to power conservation.
Leakage is wasted power that 'leaks' through the components inside the transistors on a chip.
While it is a known phenomenon, leakage is threatening future sub-65nm and low-power processors because these chips feature smaller components and significantly more transistors than previous models.
"The project will make a significant contribution in overcoming the technology shortcomings for 65nm and below, and in particular process variability and unreliability, as well as leakage currents," said lead project co-ordinator Roberto Zafalon, R&D programme manager at STMicroelectronics.
"The outcome of Clean will allow a decrease in the power consumption of nano-electronic devices and increase design productivity at the same time."
Intel admitted in November that it would be impossible to build a processor for mobile phones using current generation 65nm technology because the resulting leakage would drain the battery in minutes.
A typical desktop processor wastes about 25 per cent of its power due to leakage, according to Intel data. Processors such as the ones used in mobile phones waste up to 90 per cent and put only 10 per cent of power to good use.