A Preview of Intel's Bensley Platform (Part I)
By: David Kanter (dkanter@realworldtech.com)
Intel’s Goes Dual Core
Intel’s first foray into CMP server designs is the Paxville DP, which is currently available from the major system builders. Paxville is a shared package design that uses the Lindenhurst chipset, and to some degree it is backwards compatible with existing systems. Unfortunately, this calls attention to the main weakness of Paxville; it relies on an older system architecture that was not intended for dual core processors. While Paxville is certainly a viable upgrade path for older systems, it is quite clear that another platform will be needed to fully take advantage of dual core MPUs. That platform will be the Bensley platform.
The Bensley platform will launch in late Q1 as a combination of the Blackford chipset, the Dempsey MPU and some associated software and drivers. In early Q3, Intel will release Woodcrest, which is based on a new microarchitecture and will be a pin compatible with Dempsey. The key features which truly mark Bensley as a high performance platform are the independent front side buses, the snoop filter and the FB-DIMM memory subsystem. At the same time, Intel will also integrate many of the harder to quantify factors into the Bensley platform such as RAS and manageability features.
Dual Core Servers, Done Right
Intel’s shared bus architecture has several advantages; it is simple, easy to implement, cheap, and it is quite effective for two processor systems. However, when you have four CPUs on a single shared bus, there is not a lot of bandwidth to go around and there is an increase in cache coherency traffic to boot. All together, this makes Intel’s shared bus a suboptimal solution for four processors or more. Fortunately, Intel has gone to great lengths to address these issues in Bensley. Figure 1 below shows a comparison of the Lindenhurst platform to the Bensley platform. The initial focus will be on the buses; the memory subsystem will be discussed later.
