AlbertPacino
Skilled
Through the use of these two techniques Matrix was able to double the bit capacity using the same area of silicon, the company said.
Hybrid scaling is in essence the option to not scale parts of parts of memory design while other parts are scaled. It is the combination of different process geometries within the layers of a 3-D circuit, Matrix said. The use of hybrid scaling in the 1-Gbit ROM features logic layers manufactured at 150-nanometer rules with subsequent memory layers at 130-nm rules. Matrix claimed it was able to attain this using existing 180-nm toolsets.
This allows Matrix to shorten its development time and achieve faster time-to-market by increasing the number of memory bits possible on top of a given logic array, the company said. Matrix said it would continue to use this manufacturing approach, at progressively more advanced design rules.
The segmented wordline architecture, for which Matrix received its 100th patent, minimizes the effect of non-memory logic circuitry on silicon utilization, reducing the die's area by nearly 25 percent, Matrix claimed.
matrixsemi.com