eTernity2021
Level E
Lovely Explanation!!!! I appreciate it.So it appears that your understanding of interconnects is incomplete. Mine isn't so great either but I'll try to explain.
Think of a processor as a headmaster of a school, and the various links to it as meetings he or she has scheduled for the day. The most important meeting would be with the board of education, and then maybe some faculty members, then perhaps some custodial staff and at the very bottom of importance is you, being suspended because you didn't tuck in your shirt. The headmaster is able to meet with all of these different people, and give each person the importance that is needed. With important matters like with the board of education, the meeting is serious and prolonged. With delinquent students, it's a few seconds of yelling and then sending them home with a reprimanding letter.
So the interconnects with the processor operate in an asynchronous manner. The processor's operating speed doesn't slow down to communicate with a gen3 device, it continues to operate at it's full speed while the gen3 devices send their data, and then works with that data after it has been transferred in full. This handling of different data speeds, from the high internal frequency of the processor to the lower frequency of the interconnect, is by a part of the processor called a buffer.
In computers particularly, the analogy for 'bottleneck' is incorrectly applied to a lot of things. For a bottleneck to occur, there needs to be a constriction of flow, between two unconstricted points. There's nothing faster than gen3 at the other end of the chipset, there's just sata ports and usb. If you had a GPU attached to pcie lanes coming from the chipset, then maybe you could say the gen3 link is bottlenecking the performance of the gpu. Or in some cases, an nvme ssd that is attached to the chipset.
And that flow, must be critical to a particular operation for a bottleneck to occur. So there's no bottleneck because there's nothing that's connected to the chipset that's important enough to slow down the processor or keep it waiting.
What other components are there? If you have storage and graphics connected directly to the processor with a gen4 link, that's everything you need to have a fast and responsive system that benefits from the gen4 upgrade. You wouldn't even need the chipset if you have your peripherals attached directly to the CPU's usb ports.
And as I mentioned above, there's nothing important that is connected through the chipset that it would suffer from being a gen3 link. The gen3 link to the chipset is 32GT/s which can be translated to 32Gbps for the purposes of this explanation. What device can we have on the chipset that operates at that speed? USB gen3 2x2 tops out at 20Gbp/s. How likely is it that you'll have two of those usb controllers, operating simultaneously, at full speed?
Actual real-world performance gains is a completely different topic. It's generally accepted that there isn't much use case for gen4 today for the average user. This has been true for the early days of every generation of PCIe, except maybe gen1. But introducing gen4 to the mainstream market now gives the technology and time to mature until it actually is needed. For power users though, it's really easy to saturate a 16x gen4 link with a few ssds installed in a pcie adapter card.
i have few more doubts! please clear it!
1. as u know B550 Offers 1 GEN 4 pcie port and another 1 GEN 3 PCIE Port for GPU, if i use multiple GPUs, not SLI or CROSSFIRE, 2 independent GPUs Connected in Gen 4 first port and another one in Gen 3 port, now i am gonna do a VT-d i/o with gen 3 GPU and will attach a completely different monitor, and will redirect a VM to that GPU, as the set up is like that.
Q1) will the Gen 3 operate on x16 or will it be x8 or x4 coz, the specs says the MOBO supports x4, does that mean it supports only x4 or will it operate on x16 lanes As it is an independent GPU .
Q2) or Whenever there is multiple GPUs accomodated in 2 different GEN Ports, will they only operate in x8 lane regardless of SLI and Crossfire.
2. When we transfer data from a SATA SSD from Gen 3 NVMe port / a direct SATA Port(500MB/sec) to gen4 NVMe device, as it is obvious there will be a speed mismatch, will that be a Bottleneck or not??
3. Forgive my stupidity, Does CPU directly connects to gen 4 pcie NVMe port and the gen 4 gpu port for transmission of data, and not chipset involved as a mediator here?
4. Will GPUs have direct access to DRAMs or CPU mediates in between???