Intel Sandybridge : No OC

[asingh]

It is highly probable that the new line up from the Intel stable will not allow OC. Seems like a deliberate architecture design, and only 2-3% OC will be possible via the BCLK. All the BUS lines will be mated to a single internal clock, thus removing the external clock generator. Which literally translates to: if the memory/base clocks are tweaked then SATA, PCI, PCI-E and like wise also toggle.

Again this is speculation. Here is the article.

 

[Shripad]

Umm......

No, not exactly.

And I wont give too much importance to these things. They said same thing about Nehalem. And see where we are.

Sandybridge is suppose to have linked buses, but unlocked multipliers from earlier rumors. So should be fine.

We might not be able to get the max out of QPI / VTT buses like we can with Nehalem, but ocing shouldnt be as restricted as that articles make it out to be.

 

[comp@ddict]

Umm......

No, not exactly.

And I wont give too much importance to these things. They said same thing about Nehalem. And see where we are.

Sandybridge is suppose to have linked buses, but unlocked multipliers from earlier rumors. So should be fine.

We might not be able to get the max out of QPI / VTT buses like we can with Nehalem, but ocing shouldnt be as restricted as that articles make it out to be.

Unlocked multipliers only for some models, they will have partially unlocked and fully unlocked models(i know, it's WTF over and over again)

http://en.expreview.com/2010/07/24/intel-plans-to-limit-sandy-bridge-overclocking/8518.html