Fall IDF 2005: Intel's unified processor architecture
Contrary to some rather bizarre speculation that made its way around the 'Net, the new processor architecture that Intel announced today is a fairly conventional evolutionary step from their current offerings. Unfortunately, Intel hasn't yet announced a codename for this new architecture, so I'll refer to it as "the Merom core" from here on out.
I reported previously that the following features will define the Intel roadmap from late 2006 onward:
* Dual-core
* 64-bit support
* 65nm process technology
* Security/virtualization (i.e., Lagrande, Active Management Technology, Vanderpool, etc.)
* "Platformization" (i.e., development and marketing of CPU and feature-rich chipset combinations)
* Performance per watt
The core that will make its debut in 2H06 with Merom will embody all of the above features.
In terms of its actual implementation, the new core's microarchitecture takes the lessons learned from Netburst and the Pentium M design and combines them into a new design that can issue up to four instructions per clock to a wide, out-of-order execution core with fairly deep buffers. The two symmetric integer pipelines (compare the PM and P4's asymmetric integer pipes) for the Merom core will be 14 stages deep. (This stage count almost certainly includes the fetch and decode portion of the pipeline.) So while the Merom core is designed for better clockspeed scalability than the Pentium M, it's not at all high-clockspeed design like Netburst.
