AMD Announcements at Annual Spring Analyst Meet

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AMD Announces More K8L Details

Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap. One thing AMD representatives have not particuarly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.

A major feature of K8L is DICE, or Dynamic Independent Core Engagement. Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor. Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores. Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.

AMD Announces “Torrenza” Technology

Today AMD unveiled what it calls the evolution of enterprise level computing, called Torrenza. The new platform, says AMD, will utilize next-generation multi-core 64-bit processor that have the capability to work alongside specialized co-processors. DailyTech previously reported that AMD was considering working with co-processing design firms such as ClearSpeed, to develop and design platforms that would be able to utilize specialized processors for specific duties alongside the general host processor in a traditional Opteron socket.

With Torrenza, AMD has designed what it calls an open architecture, based on the next wave of Opteron processors, which allow what AMD calls “Accelerators.” Using the add-in accelerators, a system will be capable of peforming specialized calculations similar in fashion to the way we use GPUs today.

AMD Promises 45nm Processors By Mid-2008

65nm on track, 45nm by mid-2008

AMD is expected to increase production capacity at their Dresden Fab by four times within the next three years. The details revealed in today’s AMD Technology Analysts Day emphasize the previous announcements of upgrades and transformations of Fab 30 (soon to be Fab 38) and Fab 36. With the increased production capacity of Fab 36 AMD expects production to ramp up to 25,000 wafers per month. As AMD moves away from 200mm wafer production, 300mm wafer production is expected to completely replace 200mm production around Q2’08.

AMD Announces 4x4 Enthusiast Platform

The new 4x4 platform will feature two dual-core chips coupled with a dual-socket capable motherboard. AMD will also be releasing a new enthusiast focused chipset for the market, which is designed to take non-ECC unbuffered DDR memory. The new motherboards will be AM2 based, and take new AM2 FX-62 and higher – all AM2 Athlon FX processors will have at least two cores.

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New AMD Roadmap

Today on AMD Analyst Day, they presented their new Roadmap for 2006, 2007 and 2008.

This year AMD will shrink their processors to 65nm and as we reported introduce the “dual” Socket 4x4. In 2007 the caches should become larger and quadcore will be released. DDR3 and the next generation PCIe will be introduced in 2008. For original slides read the whole story.

New AMD mobile CPU core revealed

Other features, including those AMD cites as mobile-specific ones, are familiar from AMD’s stated plans for its next-gen quad-core desktop and server CPUs. Those include separate power planes for the two execution cores and the memory controller, the ability to halt one CPU core entirely if it’s not needed, and the dynamic link power scaling that is a part of HyperTransport 3.

That sounds an awful lot like the Turion 64 all over again—not that there’s anything wrong the Turion or with using a common CPU microarchitecture, as Intel seems to have learned through painful experience. But this talk of mobile-specific designs can get a little thick, so I pressed Hester on this point. He insisted this is a real and separate engineering effort, more so than the Turion. The distinctive mobile optimizations seem to boil down to two elements, one specific and one less so. First, AMD has redesigned the memory controller for lower power use. The Opteron memory controller has a server heritage, he said, and this reworked one will better serve the mobile market (and the desktop market, too, incidentally.) Second, Hester alluded (and this is the less specific bit) to changes in the way power is delivered throughout the chip.

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AMD 4X4 to arrive sooner rather than later

AMD REFUSED to be drawn on hard details of when it will release its 4X4 design for fast PCs aimed at gamers, but representatives said it’s likely to arrive in the near future.

The plan essentially allows motherboard manufacturers to build designs which place two two sockets next to each other, each of which holds a dual core processor.

AMD hitches wagon to a HyperTransport-powered 4x4 and K8L

At their annual spring analyst meeting yesterday, AMD fired back at Intel’s Core 2 PR blitz with a flurry of large and small announcements. A number of sites have coverage of the event in varying degrees of detail, including Realworld Technologies, Tech Report, TG Daily, CNET, the Inquirer, and Anandtech.

Below is a rundown of what was announced, along with some analysis. Hit the links above for more details.