AMD unveils 'next gen' CPU plans

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AMD confirmed details of its “Next Generation Processor Technology” today, but it’s really business as usual for the company. As AMD heads to four-core country, the company will continue to improve the bandwidth of its processor package, tweak memory and rely on help from partners to compete with an upcoming line of revamped chips from Intel.

The chips built with this design will have a few key changes over current products.

First off, AMD is touting a speedier version of HyperTransport that can handle 5.2 gigatransfers per second. The HyperTransport technology has proved key to AMD’s performance edge over Intel. AMD expects more server makers to start shipping boxes with HTX slots that allow for add-on cards to slot into the HyperTransport framework, although companies such as Sun Microsystems continue to portray HTX as a niche play for the moment.

The second major change will be the presence of shared L3 caches in AMD’s upcoming chips. AMD will continue to have “private L2 caches” but will add the on-chip L3 cache to improve overall performance.*

“We believe this strikes the right balance,” Moore said, during a speech. “This is a really interesting way to handle the memory hierarchy and it’s in stark contrast to the brute force method (used by Intel).”

Intel has relied more and more on enormous caches to improve its chips, although the company seems to be moving away from that practice in future products.

AMD has also added better power management tools, so that a system can independently power the north bridge and CPU. In addition, future chips will have twice the floating point performance, support for 1GB memory pages, DDR2 and DDR3 (when it arrives) memory support, FB-DIMM memory support and improved RAS features such as memory mirroring and memory diagnostics.

Overall, AMD is concentrating on keeping single thread software performance high, while paving the way for more multithreaded applications. Moore urged the chip industry to provide “hooks” that can make designing multithreaded applications easier.

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AMD unveils ‘next gen’ CPU plans | The Register ](AMD unveils 'next gen' CPU plans • The Register)**

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[dipdude]

Moore revealed that K8L will be the first AMD processor to have L3 cache since the K6 CPU. Each core has an independent L2 cache, but the entire processor shares an L3 cache pool. There’s no word yet on exactly how much cache the K8L can hold, though the K8L will be a 65nm SOI process so AMD engineers have a bit more die real estate to play around with.

K8L will support DDR2 and DDR3 when it becomes available, although it’s still anyone’s guess as to whether or not the market will actually adopt DDR3 quickly enough to warrant using DDR3 aggressively at the core launch. Tom Trill, Samsung’s Director of DRAM Marketing, was extremely hesitant to claim DDR3 would make it to the desktop without “significant” performance gains over DDR2 – lest anyone repeat many of the mistakes made when the industry migrated from DDR1 to DDR2.

HyperTransport 3 will be a key element of K8L. HyperTransport 3, which was just ratified a few weeks ago, increases the frequency of the current HyperTransport bus from 1.4GHz to 2.6GHz, or from 2.8GT/s to 5.2GT/s. Current AMD Opteron processors only support HT links operating at 1GHz, though the HT 2.0 specification allows these links to run as fast as 1.4GHz. Non-K8 quad core processors will almost certainly take advantage of this additional headroom as data across these links gets more crowded. However, K8L processors will have the advantage of using the full 5.2GT/s per link defined in HyperTransport 3.

DailyTech - AMD K8L: Quad Core Desktops And So Much More