One of the advantages of AMD K8 architecture is the introduction of well known HyperTransport (HT), which is a bidirectional serial/parallel high-bandwidth, low-latency computer bus. This technology is more efficient then Intel’s shared bus architecture. HyperTransport comes in three versions  1.0, Link, and 3.0  where 1.0 runs at 800MHz with a maximum data rate of 1.6GT/s (6.4GB/s) and Link runs at 1GHz with a maximum data rate of 2GT/s (8GB/s).
For the next-generation HyperTransport 3.0, which is implemented in the upcoming AMD K8L processor, its running speed is no longer fixed, but proportional to the CPU’s clock speed. HyperTransport supports up to 2.6GHz working speed, which allows for a maximum data rate of 5.2GT/s (20.8GB/s), 2.6x faster than the previous version. Yet it’s the maximum value, meaning nothing to the real situation. In real, its working speed would be 75% of the processor’s core speed, according to the specification of K8L. Taking a 2.8GHz K8L processor as an example, the HyperTransport would run at 2.8x75% = 2.1GHz, providing a maximum data rate of 2.1 x 2 = 4.2GT/s (16.8GB/s). In principle, we need a 3.5GHz processor to utilize all the bandwidth of the new HyperTransport.
HyperTransport 3.0, with no doubt, would be a wonderful design to help PCI-E 2.0, multi core, and HTX working more efficient than ever. HyperTransport3.0 is now track that NVIDIA and ATI have already announced their plan on new chipset supporting HyperTransport 3.0. NVIDIA would release the related products no after than this year, while ATI’s release is scheduled in Q2 2007. By the way, there is no any news was heard concerning HyperTransport 3.0 chipset from SiS and VIA, so far.
