CSI goes AWOL
One of the worst pieces of news to come out of Intel's October roadmap reorganization was the fact that the introduction of the company's long-planned Common System Interconnect technology would be postponed. CSI is the "HyperTransport killer" that's supposed to let Xeon and Itanium processors share the same system hardware. So CSI-based motherboards will be able to accept either a Xeon or an Itanium chip in their CPU socket with only a BIOS tweak.
CSI isn't here, though, and it won't be here this year either. Intel's next-generation x86 processors are therefore stuck with an antiquated, shared-bus interconnect topology that's bandwidth-starved, expensive, not scalable, and inferior to coherent HT in every respect.
This is bad news for those of us who're pumped about Merom/Conroe, because—as any Apple fan who uses a G4 can tell you—you can have the baddest processor on the market, but if you're starving it by sticking it on an outdated FSB then a lot of potential performance is going to waste. (Oh yes indeed my fellow Mac users; Apple is poised to have a repeat of the G4's infamous FSB bottleneck shortly after the switch to Intel. Look on the bright side, though: the situation won't be quite as dire... at first.) Furthermore, this problem gets worse rapidly as you increase the number of cores per socket.
